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MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM DESCRIPTION
This is a family of 4194304-word by 4-bit dynamic RAMS, fabricated with the high performance CMOS process, and is ideal for large-capacity memory systems where high speed, low power dissipation, and low costs are essential. The use of double-layer metal process combined with twin-well CMOS technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities.
PIN DESCRIPTION
Pin name A0 ~ A11 DQ1 ~ DQ4 RAS CAS W OE VCC VSS Function Address inputs Data inputs / outputs Row address strobe input Column address strobe input Write control input Output enable input Power supply (+5V) Ground (0V)
PIN CONFIGURATION (TOP VIEW)
FEATURES
RAS CAS access time (max.ns) Address access time (max.ns) OE access time (max.ns) Cycle time (min.ns) Power dissipation (typ.mW)
Type Name
access time (max.ns)
M5M417400CXX-5,-5S M5M417400CXX-6,-6S M5M417400CXX-7,-7S
50 60 70
13 15 20
25 30 35
13 15 20
90 110 130
655 540 475
XX=J, TP
* Standard 26 pin SOJ, 26 pin TSOP * Single 5V 10% supply * Low stand-by power dissipation 5.5mW(Max) ..................................CMOS Input level 2.2mW (Max)* ...............................CMOS Input level * Low operating power dissipation M5M417400Cxx-5,-5S .................... 800.0mW (Max) M5M417400Cxx-6,-6S .................... 660.0mW (Max) M5M417400Cxx-7,-7S .................... 580.0mW (Max) * Self refresh capability * self refresh current ................................ 200.0 A(Max) Outline 26P0D-B (300mil SOJ)
* Fast-page mode, Read-modify-write, RAS-only refresh * CAS before RAS refresh, Hidden refresh capabilities Early-write mode and OE to control output buffer impedance * All inputs, output TTL compatible and low capacitance * 2048 refresh cycles every 32ms (A0 ~ A10) *Applicable to self refresh version (M5M417400CJ,TP-5S,-6S, -7S :option) only
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
Outline 26P3D-E (300mil TSOP) NC: NO CONNECTION
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MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
FUNCTION
The M5M417400CJ,TP provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., fast page mode, RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs Operation Read Write (Early write) Write (Delayed write) Read-modify-write RAS-only refresh Hidden refresh Self refresh CAS before RAS refresh Stand-by RAS ACT ACT ACT ACT ACT ACT ACT ACT NAC CAS ACT ACT ACT ACT NAC ACT ACT ACT DNC W NAC ACT ACT ACT DNC NAC NAC NAC DNC OE ACT DNC DNC ACT DNC ACT DNC DNC DNC Row address APD APD APD APD APD APD DNC DNC DNC Column address APD APD APD APD DNC DNC DNC DNC DNC Input/Output Input OPN VLD VLD VLD DNC OPN DNC DNC DNC Output VLD OPN IVD VLD OPN VLD OPN OPN OPN Refresh YES YES YES YES YES YES YES YES NO Remark
Fast page mode identical
Note: ACT: active, NAC: nonactive, DNC: don't care, VLD: valid, IVD: invalid, APD: applied, OPN: open
BLOCK DIAGRAM
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MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IO Pd Topr Tstg Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Ta = 25C With respect to VSS Parameter Conditions Ratings -1 ~ 7 -1 ~ 7 -1 ~ 7 50 1000 0 ~ 70 -65 ~ 150 Unit V V V mA mW C C
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 ~ 70C, unless otherwise noted) (Note 1) Symbol VCC VSS VIH VIL Note 1: Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs All voltage values are with respect to VSS. Parameter Limits Min 4.5 0 2.4 -1.0** Nom 5 0 Max 5.5 0 5.5 0.8 Unit V V V V
**: VIL(min.) is -2.0V when undershoot width is less than 25ns. (Undershoot width is with respect to VSS.)
ELECTRICAL CHARACTERISTICS
(Ta = 0 ~ 70C, VCC = 5V 10%, VSS = 0V, unless otherwise noted) (Note 2) Symbol VOH VOL lOZ II ICC1(AV) High-level output voltage Low-level output voltage Off-state output current Input current Average supply current from VCC, operating (Note 3,4) ICC2 Supply current from VCC, stand-by Average supply current ICC3 (AV) from VCC, refreshing (Note 3) Average supply current ICC4 (AV) from VCC, Fast-Page-Mode (Note 3,4) Average supply current from VCC, ICC6 (AV) CAS before RAS refresh mode (Note 3) Note 2: 3: 4: M5M417400C-5,-5S M5M417400C-6,-6S M5M417400C-7,-7S (Note 5) M5M417400C-5,-5S M5M417400C-6,-6S M5M417400C-7,-7S M5M417400C-5,-5S M5M417400C-6,-6S M5M417400C-7,-7S M5M417400C-5,-5S M5M417400C-6,-6S M5M417400C-7,-7S Parameter IOH = -5.0mA IOL = 4.2mA Q floating 0V VOUT 5.5V 0V VIN 5.5V, Other inputs pins = 0V RAS, CAS cycling tRC = tWC = min. output open RAS = CAS = VIH, output open RAS = CAS VCC -0.2V RAS cycling, CAS = VIH tRC = min. output open RAS = VIL, CAS cycling tPC = min. output open CAS before RAS refresh cycling tRC = min. output open Test conditions Limits Min 2.4 0 -10 -10 Typ Max VCC 0.4 10 10 145 120 105 2 0.5 145 120 105 80 70 60 145 120 105 mA mA mA mA mA Unit V V A A
Current flowing into an IC is positive, out is negative. ICC1 (AV), ICC3 (AV), ICC4 (AV) and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open.
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MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
CAPACITANCE
(Ta = 0 ~ 70C, VCC = 5V 10%, VSS = 0V, unless otherwise noted) Symbol CI(A) CI(OE) CI(W) CI(RAS) CI(CAS) CI/O Parameter Input capacitance, address inputs Input capacitance, OE input Input capacitance, write control input Input capacitance, RAS input Input capacitance, CAS input Input/Output capacitance, data ports VI = VSS f = 1MHz VI = 25mVrms Test conditions Limits Min Typ Max 5 7 7 7 7 8 Unit pF pF pF pF pF pF
SWITCHING CHARACTERISTICS
(Ta = 0 ~ 70C, VCC = 5V 10%, VSS = 0V, unless otherwise noted, see notes 5, 12, 13) Limits Symbol Parameter M5M417400C-5,-5S Min tCAC tRAC tAA tCPA tOEA tCLZ tOFF tOEZ Note 5: Access time from CAS Access time from RAS Column address access time Access time from CAS precharge Access time from OE Output low impedance time from CAS low Output disable time after CAS high Output disable time after OE high (Note 6, 7) (Note 6, 8) (Note 6, 9) (Note 6, 10) (Note 6) (Note 6) (Note 11) (Note 11) 5 0 0 13 13 Max 13 50 25 30 13 5 0 0 15 15 M5M417400C-6,-6S Min Max 15 60 30 35 15 5 0 0 15 15 M5M417400C-7,-7S Min Max 20 70 35 40 20 ns ns ns ns ns ns ns ns Unit
An initial pause of 500 s is required after power-up followed by a minimum of eight initialization RAS cycles. The initialization cycles should be done either by RAS-only refresh cycles or by CAS before RAS refresh cycles only. Note the RAS may be cycled during the initial pause. And any 8 RAS or RAS/CAS cycles are required after prolonged periods (greater than 32ms) of RAS inactivity before proper device operation is achieved. After the initialization cycles, RAS should be kept either higher than VIH(min) or lower than VIL(max) except RAS transition time. Measured with a load circuit equivalent to 2 TTL loads and 100pF. Assumes that tRCD tRCD(max) and tASC tASC(max). Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. Assumes that tRAD tRAD(max) and tASC tASC(max). Assumes that tCP tCP(max) and tASC tASC(max). tOFF(max) and tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT | 10 A |) and is not reference to VOH(min) or VOL(max).
6: 7: 8: 9: 10: 11:
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MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Fast-Page Mode Cycles)
(Ta = 0 ~ 70C, VCC = 5V 10%, VSS = 0V, unless otherwise noted. See notes 12, 13) Limits Symbol Parameter M5M417400C-5,-5S Min tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tCDD tODD tT 13: 14: 15: 16: 17: 18: 19: Refresh cycle time RAS high pulse width Delay time, RAS low to CAS low Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low Delay time, data to CAS low Delay time, data to OE low Delay time, CAS high to data Delay time, OE high to data Transition time (Note 17) (Note 17) (Note 18) (Note 18) (Note 19) (Note 16) (Note 15) (Note 14) 30 18 10 0 10 13 0 0 8 13 0 0 13 13 1 50 10 25 37 Max 32 40 20 10 0 10 15 0 0 10 15 0 0 15 15 1 50 10 30 45 M5M417400C-6,-6S Min Max 32 50 20 10 0 10 15 0 0 10 15 0 0 15 15 1 50 10 35 50 M5M417400C-7,-7S Min Max 32 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note 12: The timing requirements are assumed tT = 5ns. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) = tRAH(min) + 2tH + tASC(min). tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. Either tDZC or tDZO must be satisfied. Either tCDD or tODD must be satisfied. tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Limits Symbol Parameter M5M417400C-5,-5S Min tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tOCH tORH Read cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time after CAS high Read hold time after CAS low Read hold time after RAS low Column address to RAS hold time CAS hold time after OE low RAS hold time after OE low (Note 20) (Note 20) 90 50 13 50 13 0 0 10 25 13 13 10000 10000 Max M5M417400C-6,-6S Min 110 60 15 60 15 0 0 10 30 15 15 10000 10000 Max M5M417400C-7,-7S Min 130 70 20 70 20 0 0 10 35 20 20 10000 10000 Max ns ns ns ns ns ns ns ns ns ns ns Unit
Note 20: Either tRCH or tRRH must be satisfied for a read cycle.
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MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Limits Symbol Parameter M5M417400C-5,-5S Min tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH tOEH Write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Write setup time before CAS low Write hold time after CAS low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low OE hold time after W low (Note 22) 90 50 13 50 13 0 8 13 13 8 0 8 13 10000 10000 Max M5M417400C-6,-6S Min 110 60 15 60 15 0 10 15 15 10 0 10 15 10000 10000 Max M5M417400C-7,-7S Min 130 70 20 70 20 0 10 20 20 10 0 15 20 10000 10000 Max ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Read-Write and Read-Modify-Write Cycles
Limits Symbol Parameter M5M417400C-5,-5S Min tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tCWL tRWL tWP tDS tDH tOEH Read write/read modify write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before W low Data hold time after W low OE hold time after W low (Note 22) (Note 22) (Note 22) (Note 21) 131 91 54 91 54 0 36 73 48 13 13 8 0 8 13 10000 10000 Max M5M417400C-6,-6S Min 155 105 60 105 60 0 40 85 55 15 15 10 0 10 15 10000 10000 Max M5M417400C-7,-7S Min 180 120 70 120 70 0 45 95 60 20 20 10 0 15 15 10000 10000 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note 21: tRWC is specified as tRWC(min) = tRAC(max) + tODD(min) + tRWL(min) + tRP(min) + 5tT. Note 22: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD(min), tAWD tAWD(min) and tCPWD tCPWD(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate.
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MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Fast-Page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle)
(Note 23) Limits Symbol Parameter M5M417400C-5,-5S Min tPC tPRWC tRAS tCP tCPRH tCPWD Fast page mode read/write cycle time Fast page mode read write/read modify write cycle time RAS low pulse width for read write cycle CAS high pulse width RAS hold time after CAS precharge Delay time, CAS precharge to W low (Note 22) (Note 24) (Note 25) 35 76 85 8 30 53 125000 12 Max M5M417400C-6,-6S Min 40 85 100 10 35 60 125000 15 Max M5M417400C-7,-7S Min 45 95 115 10 40 65 125000 15 Max ns ns ns ns ns ns Unit
Note 23: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 24: tRAS(min) is specified as two cycles of CAS input are performed. 25: tCP(max) is specified as a reference point only.
CAS before RAS Refresh Cycle
(Note 26) Limits Symbol Parameter M5M417400C-5,-5S Min tCSR tCHR tRSR tRHR CAS setup time before RAS low CAS hold time after RAS low Read setup time before RAS low Read hold time after RAS low 10 10 10 10 Max M5M417400C-6,-6S Min 10 10 10 10 Max M5M417400C-7,-7S Min 10 15 10 15 Max ns ns ns ns Unit
Note 26: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
SELF REFRESH SPECIFICATIONS
Self refresh devices are denoted by "S" after speed item, like -5S/-6S/-7S. The other characteristics and requirements than the below are same as normal devices.
ELECTRICAL CHARACTERISTICS
(Ta = 0 ~ 70C, VCC = 5V 10%, VSS = 0V, unless otherwise noted) (Note 2) Symbol Parameter Test conditions CAS before RAS refresh cycling or RAS cycling & CAS 0.2V OE & WE 0.2V or OE & WE VCC - 0.2V M5M417400C (S) A0 ~ A10 0.2V or A0 ~ A10 VCC - 0.2V tREF = 128ms (2048 cycles) output = OPEN tRAS = tRASmin. ~ 1s Average supply current from VCC Slow-Refresh cycle (Note 5) 500 Limits Min Typ Max Unit
ICC8(AV)
Average supply current from VCC Slow-Refresh cycle (Note 5)
A
ICC9(AV)
M5M417400C (S)
RAS = CAS 0.2V output = OPEN
200
A
7
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
TIMING REQUIREMENTS
(Ta = 0 ~ 70C, VCC = 5V 10%, VSS = 0V, unless otherwise noted, see notes 12, 13) Limits Symbol Parameter M5M417400C-5S Min tRASS tRPS tCHS tRSR tRHR Self Refresh RAS low pulse width Self Refresh RAS high precharge time Self Refresh RAS hold time Read setup time before RAS low Read hold time after RAS low 100 90 -50 10 10 Max M5M417400C-6S Min 100 110 -50 10 10 Max M5M417400C-7S Min 100 130 -50 10 15 Max s ns ns ns ns Unit
SELF REFRESH ENTRY & EXIT CONDITIONS
1.
In case of distributed refresh The last / first full refresh cycles (2K) must be made within tNS / tSN before / after self refresh, on the condition of tNS 32ms and tSN 32ms.
2.
In case of burst refresh The last / first full refresh cycles (2K) must be made within tNS / tSN before / after self refresh, on the condition of tNS + tSN 32ms.
8
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM TEST Mode SET Cycle
Limits Symbol Parameter M5M417400C-5,-5S Min tWSR tWHR W setup time before RAS low W hold time after RAS low 10 10 Max M5M417400C-6,-6S Min 10 10 Max M5M417400C-7,-7S Min 10 15 Max ns ns Unit
Note 27: The test mode function is initiated by a W and CAS before RAS cycle (WCBR cycle) as specified in timing diagram. The test mode function is terminated by either a CAS before RAS refresh cycle (CBR refresh cycle) or a RAS only refresh cycle. During the test mode, the device is internally organized as 16-bits wide (1M bytes depth). No addressing of CA0 and CA1 is required. During a write cycle, data must be applied to all DQ (input) pins. The data can be different between DQ pins. The data on each DQ pin is written into 4-bits memory cells, respectively. During a read cycle, each DQ (output) pin shows the test result of the 4-bits, respectively. High state indicates that they are same. Low state indicates that they are not same. During the test mode operation, only WCBR cycle can be used to perform refresh.
9
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Timing Diagrams Read Cycle
(Note 28)
10
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Write Cycle (Early Write)
11
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Write Cycle (Delayed Write)
12
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Read-Write, Read-Modify-Write Cycle
13
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
14
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM CAS before RAS Refresh Cycle, Slow Refresh Cycle
15
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 29)
Note 29: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. And in any cycle, tRSR & tRHR should be satisfied not to enter TEST MODE.
16
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Fast Page Mode Read Cycle
17
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
18
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Fast-Page Mode Write Cycle (Delayed Write)
19
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Fast Page Mode Read-Write, Read-Modify-Write Cycle
20
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Self Refresh Cycle
21
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
TEST Mode SET Cycle
Note 30:
This cycle can be used for initialized cycle after power-up, however entried into Test Mode.
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